The present invention relates to a sample-and-hold phase detector.
As illustrated in FIG. 1, a prior-art sample-and-hold phase detector comprises a current setting circuit 18 formed by a current setting resistor 13 (with value R.sub.B) which is externally connected through a terminal 12 to a PNP transistor 11. The reason for the external connection of resistor 13 will be given later. Since the voltage impressed on resistor 13 is equal to voltage V.sub.CC minus the base-emitter voltage V.sub.BE of transistor 11, an input current I.sub.B flowing through the setting resistor 13 is given by: EQU I.sub.B =(V.sub.CC -V.sub.BE)/R.sub.B ( 1)
The base of PNP transistor 11 is connected by a line 10 to the base of a PNP transistor 8 to form a current mirror circuit. The collector current I.sub.c of transistor 8 is given by: EQU I.sub.C =I.sub.B .multidot.W.sub.8 /W.sub.11 ( 2)
where W.sub.8 and W.sub.11 represent the emitter sizes of transistors 8 and 11, respectively. Transistor 8 acts as a constant current source to supply current according to a current setting signal applied to line 10 and resistor 13 acts as a first reference voltage circuit to provide a prescribed voltage corresponding to the current I.sub.B, while transistor 11 acts as a second reference voltage circuit that is responsive to that prescribed voltage to apply the current setting signal to line 10. The collector of transistor 8 is coupled through an analog switch 7 to a circuit junction 9 which is in turn connected through a storage capacitor 4 to ground, with the capacitor 4 being connected in parallel with an analog switch 6. The circuit junction 9 is further connected by an analog switch 5 to a buffer amplifier 2 whose input is also connected to ground by a capacitor 3. The output of buffer amplifier 2 is connected to the output terminal 1 of the phase detector. Amplifier 2, capacitor 3 (with value C.sub.H) and switch 5 constitute a sample-and-hold circuit. Each of the capacitors 3 and 4 is formed by an externally provided capacitor. The phase detector includes a switching circuit 17 which receives a phase reference signal (REF) from terminal 15 and an input signal from terminal 16 to generate switching signals SA, SB and SC to supply them respectively to switches 7, 6 and 5 by using a clock signal from terminal 14.
The operation of the prior art phase detector will be given below with reference to the timing diagram of FIG. 2. The input signal has an interval T seconds between successive pulses and the reference signal REF has a pulse whose leading edge is delayed by a phase difference .theta. with respect to the leading edge of the input signal and whose trailing edge occurs prior to the leading edge of the next pulse of the input signal. The switching pulse SA occurs during a period corresponding to the phase difference .theta. for operating the analog switch 7. Storage capacitor 4 is charged with a collector current supplied from transistor 8 when switch 7 is closed in response to a switching pulse SA. Capacitor 4, having a capacitance value C.sub.R, develops a voltage V.sub.CR which increases linearly with time from the leading edge of signal SIG to a maximum voltage V given by: EQU V=I.sub.C .multidot..theta..multidot.T/2.pi..multidot.C.sub.R( 3)
Substituting Equations (1) and (2) into Equation (3) gives: ##EQU1##
Switching pulse SC is a constant-duration pulse that occurs a predetermined time following the leading edge of the switching pulse SA so that switch 5 is closed briefly to transfer energy from capacitor 4 to capacitor 3 when switches 6 and 7 are in a turn-off state, whereby the voltage V is sampled by the switching pulse SC to produce a sampled voltage V'. If capacitor 3 has a sufficiently smaller capacitance value than that of capacitor 4, the sampled voltage V' is substantially equal to voltage V. The sampled voltage in capacitor 3 is delivered through buffer amplifier 2 to the output terminal 1 to indicate the phase difference between reference signal REF and input signal. The switching pulse SB occurs following the pulse SC to turn on switch 6 during the interval between a pulse SC and a pulse SA to discharge the storage capacitor 4 completely. From Equation (4), the phase-to-voltage conversion coefficient K of the prior art sample-and-hold phase detector is: EQU K=V/.theta.=k/(C.sub.R .multidot.R.sub.B) (6)
If a sample-and-hold phase detector is implemented using LSI (large scale integration) technology by integrating all resistors and capacitors, it is difficult to provide a precision phase detector due to large variabilities of resistance and capacitance values, typically .+-.30% deviations from the rated value. Thus, for LSI implemented phase comparators, resistor 13 and capacitors 3, 4 are provided by elements located outside of the LSI chip to ensure a high level of precision.
It is desirable, however, to reduce the number of external connections since the number of terminals available in an LSI chip is severely limited. It is further desirable from the noise view point that the values of capacitors 3 and 4 be as large as possible while the value of current setting resistor 13 be as small as possible. However, this results in an increase in currents I.sub.B and I.sub.C as seen from Equations (1) and (2).